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Category:
Language:
English
Total Size:
595.2 MB
Info Hash:
47A78A95DFA3A4B293CE07513D9ACDE273FF6439
Added By:
Added:
Jan. 11, 2024, 5:13 p.m.
Stats:
|
(Last updated: May 6, 2025, 1:58 p.m.)
| File | Size |
|---|---|
| Get Bonus Downloads Here.url | 182 bytes |
| 1 - Introduction.mp4 | 22.5 MB |
| 2 - AMBA introduction.mp4 | 6.3 MB |
| 3 - Comparision between AHB AXI APB.mp4 | 12.9 MB |
| 10 - Read process Timing diagram.mp4 | 15.1 MB |
| 11 - Dependencies between channel handshake signals.mp4 | 10.9 MB |
| 4 - Introduction to AXI.mp4 | 6.1 MB |
| 5 - AXI channel Architecture of Readwrites.mp4 | 17.6 MB |
| 6 - AXI signals.mp4 | 12.0 MB |
| 7 - Handshaking signals.mp4 | 12.0 MB |
| 8 - Signal Diagram.mp4 | 20.0 MB |
| 9 - Write process Timing diagram.mp4 | 12.1 MB |
| 12 - AXI state machine for write read.mp4 | 2.4 MB |
| 13 - AXI MasterSlave Block diagram and Writeread process.mp4 | 11.1 MB |
| 14 - Design of AXI bus using verilog HDL write process.mp4 | 279.4 MB |
| 14 - axi-master-write.v | 3.1 KB |
| 14 - axi-slave-write.v | 2.7 KB |
| 15 - Design of AXI bus using verilog HDL Read process.mp4 | 123.3 MB |
| 15 - axi-master-read.v | 2.5 KB |
| 15 - axi-slave-read.v | 2.2 KB |
| 16 - AXI master slave.mp4 | 12.8 MB |
| 16 - axi-master.v | 1.6 KB |
| 16 - axi-slave.v | 1.5 KB |
| 17 - Test bench simulation.mp4 | 19.0 MB |
| 17 - design.sv | 188 bytes |
| 17 - testbench.sv | 2.3 KB |
| Bonus Resources.txt | 386 bytes |
Name
DL
Uploader
Size
S/L
Added
-
595.2 MB
[15
/
3]
2024-01-11
| Uploaded by FreeCourseWeb | Size 595.2 MB | Health [ 15 /3 ] | Added 2024-01-11 |
-
851.0 MB
[12
/
6]
2023-06-20
| Uploaded by nehalpuja | Size 851.0 MB | Health [ 12 /6 ] | Added 2023-06-20 |
NOTE
SOURCE: Simple Axi Bus Design Using Verilog Hdl DevCourseWeb
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MEDIAINFO
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